1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage device in which a polysilicon SOI layer is used as an active area.
2. Description of the Related Art
A silicon-on-insulator (SOI) substrate must be used to realize a decanano-scale semiconductor device that has been actively developed in recent years. However, since the SOI substrate is expensive, a technology using polysilicon as an SOI layer has been studied (see, e.g., S. S. Bhattacharya, et al., IEEE Trans. ED41, no. 2, pp 221-237, 1994). Although a basic structure of a transistor to be used is very similar to that of a thin film transistor (TFT) used for, e.g., a display, and a TFT for a display panel has been also miniaturized to realize a system-on-panel (SOP). For such circumstances, a miniaturized TFT used in an SOP is getting closer to a decanano-scale semiconductor device using a polysilicon layer. In such a trend, a technology of also using a memory in an SOP has been also studied.
However, the polysilicon has a problem that conduction electrodes are scattered at a grain boundary between grains. A particle diameter of a general silicon grain for this type of application is 100 to 300 nm, and unavoidable unevenness occurs in device characteristics depending on whether a grain boundary between grains is included in a channel region. Further, deterioration of an S-factor (an inverse number of an inclination of a sub-threshold current with respect to a gate voltage) due to miniaturization produces a risk in a device operation itself.
As explained above, a decanano-scale polysilicon SOI device (a non-volatile memory in particular) has a problem of unevenness in characteristics due to a grain boundary of the polysilicon. Therefore, realization of a non-volatile semiconductor storage device and a manufacturing method thereof that suppress unevenness in characteristics due to a grain boundary and have an improved S-factor has been demanded.